Gate stress test of a MOS memory

Details Gate stress test of a MOS memory Gate stress test of a MOS memory

1986-12-22

1988-06-14

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365230, 371 21, G11C 700

Patent

active

047516798

ABSTRACT:
A dynamic random access memory, formed in a substrate, has an array comprised of intersecting rows and columns with memory cells at intersections thereof. Along each row is a plurality of memory cells. Each memory cell has a storage capacitor and a transfer device. The transfer device is a transistor which has gate to which is applied a voltage to select the memory cell. Each transfer device has an insulator between the its gate and the substrate. During a test mode of the memory, all of the transfer gates are subjected to a stress test of this insulator to provide an accelerated test for the integrity of this insulator.

REFERENCES:
patent: 4527254 (1985-07-01), Ryan et al.
patent: 4597062 (1986-06-01), Asano et al.

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