Address buffer circuit for a dram

Details Address buffer circuit for a dram Address buffer circuit for a dram

1986-12-22

1989-01-24

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365230, 365203, G11C 700, G11C 800

Patent

active

048005312

ABSTRACT:
A DRAM has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh control circuit has an output which is also clocked to the latch. The latch provides an internal address signal for selecting a word line. The internal address signal is representative of the output of the NOR gate when the DRAM is running a data cycle and is representative of the output of the refresh control circuit when the DRAM is running a refresh cycle.

REFERENCES:
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4677593 (1987-06-01), Davis
patent: 4712197 (1987-12-01), Sood

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