4. Error detection/correction and fault detection/recovery
  5. Data processing system error or fault handling
  6. Reliability and availability

Robert Joersz

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Address assignment to transaction for serialization

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hazard queue for transaction pipeline

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Local region table for storage of information regarding...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple-stage pipeline for transaction conversion

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Non-inline transaction error correction

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Profile ID: LFUS-PAI-P-2420175

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