Multiple-stage pipeline for transaction conversion

Details Multiple-stage pipeline for transaction conversion Multiple-stage pipeline for transaction conversion

2007-04-24

2007-04-24

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

10334855

ABSTRACT:
A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.

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Berg et al; “Critical Review of Programmable Mediaprocessor Architectures,” SPIE Proceedings, vol. 3655, pp. 147-156, 1999.

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