Hazard queue for transaction pipeline

Details Hazard queue for transaction pipeline Hazard queue for transaction pipeline

2006-02-07

2006-02-07

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S108000, C711S140000, C711S169000, C712S216000, C712S217000, C712S218000, C712S219000

Reexamination Certificate

active

06996665

ABSTRACT:
A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

REFERENCES:
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patent: 6417848 (2002-07-01), Battle
patent: 6457131 (2002-09-01), Kuemerle
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Microsoft Press, Computer Dictionary, 1997, 3rdedition, pp 215.

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