Address assignment to transaction for serialization

Details Address assignment to transaction for serialization Address assignment to transaction for serialization

2006-02-14

2006-02-14

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S147000, C707S793000, C712S218000

Reexamination Certificate

active

07000089

ABSTRACT:
The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.

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patent: 6088800 (2000-07-01), Jones et al.
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6154816 (2000-11-01), Steely et al.
patent: 6321303 (2001-11-01), Hoy et al.
patent: 6434699 (2002-08-01), Jones et al.

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