4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Memory testing

Paul Stanley Hughes

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Integrated circuit and method for testing memory on the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Memory testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Supporting scan functions within memories

Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate

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Synchronisation of signals between asynchronous logic

Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2263131

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