Memory testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

C714S733000

Reexamination Certificate

active

08006144

ABSTRACT:
This application discloses a data processing apparatus comprising: at least one memory; processing logic operable to perform data processing operations on data and operable to access said at least one memory; and memory testing logic operable to perform a transparent algorithm testing routine on said at least one memory, said data processing apparatus impeding said processing logic from accessing said at least one memory while said memory testing logic is performing said testing routine; wherein said processing logic and said memory testing logic are operable to detect a system event, said memory testing logic being operable when performing said testing routine to respond to detection of said system event by stopping said testing routine and restoring said at least one memory to an initial state, said initial state being a state it was in immediately prior to commencement of said testing routine, whereupon said data processing apparatus is operable to allow said processing logic to access said at least one memory.

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Boutobza, et al. “A Transparent based Programmable Memory BIST”, 11thEuropean Test Symposium, May 21-24, 2006; pp. 89-96, IEEE Computer Society, 2006.

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