Synchronisation of signals between asynchronous logic

Details Synchronisation of signals between asynchronous logic Synchronisation of signals between asynchronous logic

2005-12-22

2009-02-10

Lugo, David B (Department: 2611)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C375S371000

Reexamination Certificate

active

07489752

ABSTRACT:
A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchronizer operable to synchronize a signal processed by said first logic to produce a signal synchronized to said second clock domain; a synchronized signal output operable to export from said data processor said synchronized signal output from said synchronizer; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronized signals from each of said plurality of data processors and to combine said exported synchronized signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.

REFERENCES:
patent: 6424179 (2002-07-01), Stevens
patent: 2007/0113230 (2007-05-01), Bourdon et al.

Affiliated with

Also associated with

Rating

Synchronisation of signals between asynchronous logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronisation of signals between asynchronous logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronisation of signals between asynchronous logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4080760