Test circuit for delay lock loops

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage

Reexamination Certificate

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C327S158000

Reexamination Certificate

active

07061224

ABSTRACT:
A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.

REFERENCES:
patent: 6304116 (2001-10-01), Yoon et al.
patent: 6788594 (2004-09-01), Ware et al.
patent: 6798186 (2004-09-01), Korger et al.
patent: 6844761 (2005-01-01), Byun et al.
patent: 6850051 (2005-02-01), Roberts et al.
patent: 6876186 (2005-04-01), Gupta
patent: 2004/0239389 (2004-12-01), Matsuno

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