Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1995-06-30
1997-11-11
Nguyen, Vinh P.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324765, 324537, G01R 3102
Patent
active
056868430
ABSTRACT:
Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.
REFERENCES:
patent: 4220917 (1980-09-01), McMahon, Jr.
patent: 4441075 (1984-04-01), McMahon
patent: 5047711 (1991-09-01), Smith et al.
patent: 5397997 (1995-03-01), Tuckerman et al.
patent: 5426566 (1995-06-01), Beilstein, Jr. et al.
patent: 5502333 (1996-03-01), Bertin
Beilstein, Jr. Kenneth Edward
Bertin Claude Louis
Dubois Dennis Charles
Howell Wayne John
Kelley, Jr. Gordon Arthur
International Business Machines - Corporation
Nguyen Vinh P.
LandOfFree
Methods and apparatus for burn-in stressing and simultaneous tes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for burn-in stressing and simultaneous tes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for burn-in stressing and simultaneous tes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1232127