Scannable latch for a dynamic circuit

Details Scannable latch for a dynamic circuit Scannable latch for a dynamic circuit

2002-01-30

2003-05-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S016000, C326S095000, C326S098000, C714S724000

Reexamination Certificate

active

06570407

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (
10
).
Integrated circuits (“ICs”), such as the ones shown in
FIG. 1
, often have a number of storage elements, e.g., latches and flip-flops, that store logical states (e.g., HIGH and LOW represented as a “1” and “0,” respectively) within the integrated circuit. In normal operation, data from a computer system component is received by one or more storage elements and then is outputted to the same and/or another computer system component.
FIG. 2
shows a commonly used type of storage element known in the art as a “domino gate” (
11
). The domino gate (
11
) has a dynamic input stage (
13
) and a static output stage (
15
). A clock signal (shown in
FIG. 2
as CLK and also referred to as “reference clock”) serves as an input to the dynamic input stage (
13
) and essentially “clocks” the domino gate (
11
). Further, the domino gate (
11
) has a first input signal (shown in
FIG. 2
as INPUT_A), and a second input signal (shown in
FIG. 2
as INPUT_B). Although
FIG. 21
shows the domino gate (
11
) having only two inputs, other conventional domino gates may have different amount of input signals.
The operation of the domino gate (
11
) is as follows. When the clock signal is low, a dynamic node (shown in
FIG. 2
as DYNAMIC_NODE) is precharged high through a transistor (
17
), and an output node (shown in
FIG. 2
as OUT) of the domino gate (
11
) is set to low via an inverter (
19
) in the static output stage (
15
). The period in which the clock signal is low is referred to as the “precharge phase.” A rising transition on the clock signal conditionally discharges the dynamic node through a pulldown network formed by a series of transistors (
20
,
22
,
24
). The values of the input signals determine whether the discharge actually takes place. The period in which the clock signal is high is referred to as the “evaluation phase.”
Once the dynamic node is discharged, it will remain low for the rest of the evaluation phase no matter what values the input signals assume after the start of the evaluation phase. Therefore, either the input signals have to settle to their stable values before the start of the evaluation phase or they can settle to a stable high value by making a single rising transition during the evaluation phase.
The inverter (
19
) in the static output stage (
15
) is included in the domino gate (
11
) for several reasons. First, it is required for proper operation of a series of domino gates (
11
). Secondly, because the dynamic node is a weak node, the inverter (
19
) separates the dynamic node from components connected to the domino gate (
11
), alleviating charge-sharing problems and minimizing capacitive coupling.
Because the precharge and evaluation of a domino gate is initiated by a reference clock, uncertainty at the beginning of the rising and falling edge of the reference clock reduces the actual usable time period for operation of a path formed by a series of domino gates. To decrease, or eliminate, the impact of reference clock uncertainty, a special element, such as a latch (
34
), as shown in
FIG. 3
a,
sequentially follows one or more domino gates.
FIG. 3
b
shows a circuit schematic of the typical latch (
34
) for a dynamic circuit. Because the latch (
34
) does not input the reference clock, it is able to capture the result from a dynamic input stage of a domino circuit after the reference clock initiates the evaluation phase. The time between when the reference clock initiates the evaluation phase and the last moment the latch is able to capture the result from the dynamic input stage of the domino circuit is referred to as an “opportunistic time borrowing window.” The end of this opportunistic time borrowing window is determined by the start of the precharge phase. By using a delay element (
36
) to set the opportunistic time borrowing window slightly wider than the reference clock uncertainty, the latch (
34
) is able to regain the time loss of actual usable time caused by reference clock uncertainty.
In order to test the function of one or more dynamic gates, e.g., domino gates, a “scan test” methodology may be used. Generally, in the scan test methodology, sequential elements are connected in a circuit device or element by using a register like chain known as a “scan path.” To begin the “shift,” a storage element in the scan path is tapped, that is, selected as the point at which to shift in controlled test bits. Similarly, a sequence of bits may be shifted out from the circuit device at a selected point further down the chain and compared with an expected output. This technique of shifting test data bits in and out is known as “scanning.”
However, although including a set-reset flip flop, or other equivalent latch, is desirable in order to reduce domino gate failure, implementing a scan chain to the latch has proven to be extremely challenging because incorporating scan functionality to the set-reset flip flop is very difficult to put into actual practice. Thus, there is a need for a scan capable flip-flop or latch device that can be implemented into a dynamic circuit.
SUMMARY OF INVENTION
According to one aspect of the present invention, an apparatus for scanning a test data sequence into a circuit path comprises a dynamic input stage that receives at least one input during a normal operation, a scannable shadow latch that holds an evaluation result of a circuit in the circuit path, and a logic gate that receives an output from the dynamic input stage and an output from the shadow latch, where the logic gate generates an output of the apparatus, and where, during a scan operation, the scannable shadow latch receives the test data sequence
According to another aspect, a scannable latch positioned in a circuit path comprises means for receiving a normal operation input sequence, means for receiving a scan operation input sequence, and means for selecting the input to the circuit path from among the normal operation input sequence and the scanning operation input sequence.
According to another aspect, a method of scanning a test data sequence into a circuit path comprises disabling a normal operation of an input circuit, wherein the input circuit comprises a dynamic input stage and a shadow latch, inputting a scanning operation input sequence into the shadow latch, wherein the shadow latch generates an output, and inputting the shadow latch output to the circuit path.
According to another aspect, a method of scanning a test data sequence into a circuit path comprises a step for disabling a normal operation of an scannable latch, a step for inputting scan test data into a shadow latch during a scan operation, wherein a shadow latch generates an output thereupon, and a step for generating an input to the circuit path from the shadow latch, where the scannable latch comprises the dynamic input stage and the shadow latch.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 6085343 (2000-07-01), Krishnamoorthy
patent: 6252417 (2001-06-01), Adams et al.

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