Joe M. Jeddeloh

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Embedded processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Interface for high speed memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent

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Interface for high speed memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent

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Memory device interface methods, apparatus, and systems

Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate

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Method and system for concurrent computer transaction processing

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent

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Profile ID: LFUS-PAI-P-658522

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