Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-12-22
2001-12-11
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S601000
Reexamination Certificate
active
06330681
ABSTRACT:
The present invention generally relates to digital circuits and, more specifically, to a mechanism for modifying the power consumption and noise conditions of a digital circuit (or system) under test. It is more specifically applicable to circuits implementing built-in self-test (BIST).
BACKGROUND OF THE INVENTION
The behavior of a circuit under test is often modified to increase the level of activity of all its components to facilitate testing of the circuit. However, the reconfigured circuit might consume an average amount of power that is significantly higher from that measured during normal operation for the same clock frequency. This is especially true when the circuit is tested at high-speed to detect defects that might cause delay faults, for example. Excessive power consumption due to the increased circuit activity (or toggle rate) can damage the circuit itself or the test equipment and it can also invalidate the results of the test.
The additional stress caused by a controlled amount of additional power consumption can, however, be used to evaluate the reliability of the circuit. It allows the temperature of the circuit to be increased without requiring additional equipment (e.g. hot chuck, furnace). The elevated temperature is known to reduce the performance of a circuit. This kind of test is used to screen circuits that must be able to function at high temperature.
Jaber et al U.S. Pat. No. 5,614,838 discloses a reduced power apparatus and method for testing high speed components. The method is only applicable to a specific type of circuit known as Level-Sensitive Scan Design (LSSD), where separate clock sources are needed to control the circuit in normal and test modes of operation. Even though the patentee claims that the method is applicable to other types circuits, it is neither obvious nor practical to use the method for circuits other than LSSD circuits. In general, only one clock is available for controlling normal and test modes of operation (e.g. multiplexed scan). Therefore, it is not possible to gate the clock during the shift operations. Also, the method does not allow adjustment of the level of power consumption, which might invalidate the performance test results.
SUMMARY OF THE INVENTION
The present invention is used in combination with BIST methods for controlling the amount of power consumption of a digital circuit or system under test. Since the power level can, in many cases, be made proportional to the test clock or frequency for a given set of environmental conditions such as supply voltage and temperature, the present invention proposes a flexible programmable clock control mechanism allows the average power consumption to be set by suppressing clock pulses during the phases of the test that do not require the maximum level of activity. In other phases of the circuit where the performance of the circuit is being evaluated, no clock pulses are suppressed so that the conditions are close as possible, if not identical, to the normal mode of operation. The programmability is necessary in order to test the circuit under various sets of conditions that occur at different times in the life cycle of the circuit under test (e.g. wafer probe, package test, board manufacturing, system burn-in, field maintenance) using only available system clocks.
The present method is compatible with Phase-Locked Loop (PLLs) used to synchronize the circuit with other circuits of the system and as a clock multiplier. The method can also be used with several known BIST methods such as those disclosed in U.S. Pat. Nos. 5,329,533 (Lin), 4,503,537 (McAnney), 5,349,587 (Nadeau-Dostie et al), 4,969,148 (Nadeau-Dostie et al) and co-pending application Ser. No. 08/752,499 (Nadeau-Dostie et al), incorporated herein by reference. For each of these methods, there is an interval of time in which the clock should not be suppressed in order to evaluate the performance of the circuit under test is or can be generated.
One aspect of the present invention is generally defined as an improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.
Another aspect of the present invention is generally defined as a clock controller for use during testing of a digital circuit or system, comprising means responsive to a reference clock applied to the controller for generating a test clock signal for use by the digital circuit; the means including means responsive to a first value of a test phase signal for periodically suppressing clock cycles from the reference clock so as to operate the circuit a lower power level than a maximal power level and responsive to a second value of the test phase signal for not suppressing clock cycles from the reference clock so as to operate the circuit at the frequency of the reference clock.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5329533 (1994-07-01), Lin
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5655127 (1997-08-01), Rabe et al.
patent: 6037813 (2000-03-01), Eto et al.
Cote Jean-Francois
Gauthier Pierre
Nadeau-Dostie Benoit
Heckler Thomas M.
LogicVision, Inc.
Ross P.C. Sheridan
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