4. Active solid-state devices (e.g., transistors, solid-state diode
  5. Housing or package
  6. Multiple housings

Jae Weon Cho

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Fabrication method for chip size semiconductor package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Patent

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LOC (lead on chip) package and fabricating method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Patent

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Stacking type semiconductor chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Patent

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Wire bonding wedge tool with electric heater

Electric heating – Heating devices – Tool or instrument
Patent

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Profile ID: LFUS-PAI-P-775142

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