LOC (lead on chip) package and fabricating method thereof

Details LOC (lead on chip) package and fabricating method thereof LOC (lead on chip) package and fabricating method thereof

1996-01-19

1998-11-10

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

257687, 257787, 257666, H01L 23495, H01L 2322, H01L 2324, H01L 2828

Patent

active

058348301

ABSTRACT:
An LOC semiconductor package includes: a semiconductor chip; a plurality of two-sided tapes being attached on predetermined portions of the semiconductor chip inthe form of layers; a lead frame having a step coverage corresponding to the form of the two-sided tape; wires electrically connecting inner leads of the lead frame to pads of the semiconductor chip; and a coating fluid for covering the semiconductor chip, the lead frame and the wires. Its fabricating method includes the steps of: forming an LOC lead frame having dam bars for a chip size package; attaching a plurality of two-sided tapes on the dam bars of the lead frame in the form of layers; attaching a semiconductor chip onto an uppermost layer of said plurality of two-sided tapes; wire-bonding a pad of the semiconductor chip to respective inner leads of the lead frame by using a conductive means; and potting to inject a coating fluid into the lead frame. By employing the LOC package and its fabricating method, the fabricating process can be simplified and its production cost can be reduced.

REFERENCES:
patent: 5583375 (1996-12-01), Tsubosaki et al.
patent: 5585600 (1996-12-01), Froebel et al.

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