Fabrication method for chip size semiconductor package

Details Fabrication method for chip size semiconductor package Fabrication method for chip size semiconductor package

1998-03-31

1999-08-03

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

438106, 438121, H01L 2144, H01L 2148, H01L 2150

Patent

active

059337117

ABSTRACT:
A fabrication method for a chip size semiconductor package, includes providing a conductive package frame having a plurality of paddles which are each supported from the frame by a plurality of tie bars, adhering a semiconductor chip to each paddle, connecting each of the semiconductor chips to the frame by a plurality of wires, plating a conductive material onto each wire, forming an insulating layer on a surface of each semiconductor chip, cutting each wire to form a lead, and removing the plurality of tie bars to separate the completed package from the frame.

REFERENCES:
patent: 5476211 (1995-12-01), Khandros
patent: 5480841 (1996-01-01), Bickford et al.
patent: 5683944 (1997-11-01), Joiner et al.
patent: 5731231 (1998-03-01), Miyajima

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