Method of HDL simulation considering hard macro core with...

Details Method of HDL simulation considering hard macro core with... Method of HDL simulation considering hard macro core with...

2007-05-01

2007-05-01

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10867726

ABSTRACT:
A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup time and/or hold time to be interpreted as zero. A setup time and/or hold time may be negative relative to a particular clock cycle while being positive relative to another clock cycle. Incorporating the value of the negative setup time and/or hold time without altering its value to zero may increase the accuracy of HDL simulations.

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patent: 6367060 (2002-04-01), Cheng et al.
patent: 1999-0079355 (1999-11-01), None

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