Cache memory and control method thereof

Details Cache memory and control method thereof Cache memory and control method thereof

2006-05-16

2006-05-16

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

07047363

ABSTRACT:
A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises a tag memory1for storing an address tag of an address of a cache data and a first valid bit for showing the presence of validity of the cache data in a set of blocks in response to an index, and a valid bit register2for storing a second valid bit corresponding to the first valid bit, and resetting the second valid bit, and the valid bit is generated based on the first valid bit and the second valid bit.

REFERENCES:
patent: 2-90348 (1990-03-01), None

Affiliated with

Also associated with

Rating

Cache memory and control method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory and control method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory and control method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3561758