4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Replacement of memory spare location, portion, or segment

Gregory J. Fredeman

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Apparatus and method for improving sensing margin of...

Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate

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Column redundancy architecture system for an embedded DRAM

Static information storage and retrieval – Read/write circuit – Bad bit
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Command multiplier for built-in-self-test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Design structure for improving sensing margin of...

Static information storage and retrieval – Read/write circuit – Having fuse element
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Dynamic random access memory with smart refresh scheduler

Static information storage and retrieval – Read/write circuit – With shift register
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Profile ID: LFUS-PAI-P-2423395

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