Dynamic random access memory with smart refresh scheduler

Details Dynamic random access memory with smart refresh scheduler Dynamic random access memory with smart refresh scheduler

2005-10-11

2005-10-11

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

With shift register

C365S222000, C365S230030

Reexamination Certificate

active

06954387

ABSTRACT:
In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

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