Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-03-29
2002-09-03
Elms, Richard (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070, C365S230060
Reexamination Certificate
active
06445626
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width.
BACKGROUND OF THE INVENTION
Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, DRAMs are made of a plurality of blocks or micro-cells. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16X to 256X) than that of a bank of a conventional stand-alone DRAM. Only one block of the eDRAMs is activated each time. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
In order to effectively utilize the large DRAM cache size, a small SRAM unit about the same size of an eDRAM block is used. The SRAM unit serves as a cache interface between an eDRAM and processor(s). The wide internal bus is used for transferring data among eDRAM, SRAM and the processor(s). More specifically, data residing in eDRAM memory cells coupled to a wordline traversing an eDRAM block is transferred to primary sense amplifiers. The data is then transferred to corresponding secondary sense amplifiers. The data is then transferred to the SRAM and stored in the memory cells thereof at the same wordline location. A TAG memory records the block address of the data stored within the SRAM. The data is then transferred to the processor(s).
Generally, neither column addressing nor column decoding is provided for the wide bandwidth eDRAM configuration, since they are not necessary. Hence, a main challenge of the wide bandwidth eDRAM configuration is to provide an effective column redundancy scheme to repair defective column elements without using column addressing. Most of the conventional DRAM approaches require a column address to indicate the location of failed column elements requiring repair.
In a conventional DRAM array, bitline pairs are grouped hierarchically by column address. Only one data bit from a group of bitlines is selected to be transferred via the local and global datalines each time. Therefore, the most common redundancy approach for the conventional DRAM is to provide repair for whole group of bitlines using the column address.
This approach does not lend itself to a wide bandwidth eDRAM, because data from every pair of bitlines of the eDRAM is simultaneously accessed. Further, since all the datalines are coupled to the eDRAM, the data from every pair of bitlines is simultaneously transferred to SRAM; and since all the datalines are coupled to the SRAM, the data from the SRAM is all simultaneously transferred to the processor(s). For such a one-to-one wiring configuration, if any of the datalines fail and no redundancy is offered, the chip must be discarded. If, however, redundancy bitlines are provided in the wide bandwidth eDRAM, it is not easy to correctly replace the failed pair of bitlines without affecting the integrity of the data. Additionally, it is difficult to locate the failed pair of bitlines in the wide bandwidth eDRAM, since, as noted above, column addressing is not available for the wide bandwidth eDRAM.
SUMMARY
An aspect of the present invention is to provide a column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width.
Another aspect of the present invention is to provide a column redundancy architecture system for an eDRAM having a self-diagnostic system for testing column redundancy elements of the architecture system.
Accordingly, a column redundancy eDRAM architecture system for an embedded DRAM having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
Testing of the redundancy dataline column is done by first testing the non-redundancy dataline columns and then testing the redundancy dataline column. A logic high valid bit is stored within the memory device to indicate whether the redundancy of a particular micro cell block MCB of the eDRAM is being used or not. The valid bit allows the data to bypass the redundancy reroute mechanism being used, if the valid bit indicates that the redundancy is not being used.
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patent: 6400619 (2002-06-01), Hsu et al.
Fredeman Gregory J.
Hsu Louis L.
Joshi Rajiv V.
Dilworth & Barrese LLP
Elms Richard
IBM Corporation
Nguyen Hien
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