Circuit for the generation of a scanning clock in an operational

Details Circuit for the generation of a scanning clock in an operational Circuit for the generation of a scanning clock in an operational

1991-12-18

1993-06-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307269, 328105, 328153, H03K 19096

Patent

active

052202178

ABSTRACT:
The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

REFERENCES:
patent: 4413077 (1985-01-01), Agrawal et al.
patent: 4441182 (1984-04-01), Best et al.
patent: 4627085 (1986-12-01), Yuen
patent: 4649539 (1987-03-01), Crain et al.
patent: 4701920 (1987-10-01), Resnick et al.
IBM Technical Disclosure Bulletin; vol. 31, No. 4; Sep. 1988 "LSSD Compatible Non-Overlapping Clock Splitter".

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