4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Replacement of memory spare location, portion, or segment

Donald A. Priore

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Architectures for a single-stage grooming switch

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate

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Bitcell simulation device and methods

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
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Digital communications processor

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate

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Embedded RAM with self-test and self-repair with spare rows...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Encoding of failing bit addresses to facilitate multi-bit failur

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Profile ID: LFUS-PAI-P-1833528

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