Architectures for a single-stage grooming switch

Details Architectures for a single-stage grooming switch Architectures for a single-stage grooming switch

2002-01-17

2004-10-19

Chin, Wellington (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S360000

Reexamination Certificate

active

06807186

ABSTRACT:

BACKGROUND OF THE INVENTION
Telecommunications channels often carry traffic that is multiplexed from several sources. For example, a 2.488 Gb/s SONET STS-48 channel carries 48 51.84 Mb/s SONET STS-1 channels that are time multiplexed on a byte-by-byte basis. That is, the channel carries bytes 1.1, 2.1, 3.1, . . . , 48.1, 1.2, 2.2, 3.2, . . . , 48.2, 1.3, 2.3, 2.3, . . . where n.m denotes byte m of subchannel n. Details of the SONET format can be found in Ming-Chwan Chow, Understanding SONET/SDH: Standards & Applications, Andan Pub, ISBN 0965044823, 1995 and in ANSI Standard T1.105-1995.
An STS-1 SONET frame is a repeating structure of 810 bytes arranged into 9 rows of 90 columns. The frame structure is transmitted in row-major order. That is, all 90-bytes of row 0 are transmitted, then all 90 bytes of row 1, and so on. At higher multiplexing rates, each byte of the STS-1 frame is replaced by a number of bytes, one from each of several multiplexed sources. For example, at STS-48, 48 bytes, one from each of 48 STS-1 subframes, are transmitted during each column interval. In this case, the order of transmission is to send all 48 subframe bytes for one column before moving on to the next column and to send all of the columns of a row before moving on to the next row.
A digital cross connect is a network element that accepts a number of multiplexed data channels (e.g., 72 STS-48 channels) and generates a number of multiplexed output channels where each output channel carries an arbitrary set of the subchannels from across all of the input ports. For example, one of the STS-48 output channels may contain STS-1 channels from different input channels in a different order than they were originally input.
An example of digital cross connect operation is shown in FIG.
1
. The figure shows a cross connect
30
with two input ports and two output ports. Each of these ports contains four timeslots. Input port
1
(the top input port) carries subchannels A, B, C, and D in its four slots and input port
2
(the bottom port) carries subchannels E, F, G, and H in its four timeslots. Each timeslot of each output port can select any timeslot of any input port. For example, output port
1
(top) carries subchannels H, D, F, and A from 2.4, 1.4, 2.2, 1.1 where x.y denotes input port x, timeslot y. Input timeslot must be switched in both space and time. The first timeslot of output port
1
, for example, must be switched in time from slot
4
to slot
1
and in space from port
2
to port
1
. Also, some timeslots may be duplicated (multicast) and others dropped. Subchannel A, for example, appears in output timeslots 1.4 and 2.2 and subchannel G is dropped, appearing on no output timeslot.
A digital cross connect can be implemented in a straightforward manner by demultiplexing each input port, switching all of the timeslots of all of the input ports with a space switch, and then multiplexing each output port. This approach is illustrated in FIG.
2
. The four timeslots of input port
1
are demultiplexed in demultiplexers (Demux)
32
such that each is carried on a separate line. All of these demultiplexed lines are then switched by a space switch
34
to the appropriate output timeslots. Finally, a set of multiplexers (Mux)
36
multiplexes the timeslots of each output channel onto each output port. This approach is used, for example, in the systems described in U.S. Pat. Nos. 3,735,049 and 4,967,405.
The space-switch architecture for a digital cross connect as shown in
FIG. 2
has the advantage that it is conceptually simple and strictly non-blocking for arbitrary unicast and multicast traffic. However, it results in space switches that are too large to be economically used for large cross connects. For example, a digital cross connect with R=72 ports and T=48 timeslots requires a RT×RT (3456×3456) space switch with R
2
T
2
=11,943,936 cross points. Further, this large switch will be operated at a very slow rate. It will only need to switch a new batch of input timeslots after T bytes have been received. Thus, it operates at 1/T the byte rate.
A more economical digital cross connect can be realized using a three-stage time-space-time (T-S-T) switch architecture as illustrated in FIG.
3
. Here each input port is input to a time-slot interchanger (TSI)
38
. A TSI switches a multiplexed input stream in time by interchanging the positions of the timeslots. To switch time-slot i to time-slot j, for example, slot i is delayed by T+j−i byte times. The multiplexed streams out of the input TSIs are then switched by a R×R space switch
40
that is reconfigured on each timeslot. The outputs of this space switch are switched in time again by a set of output TSIs
42
. This T-S-T architecture is employed, for example, by the systems described in U.S. Pat. Nos. 3,736,381 and 3,927,267.
An example of the operation of a T-S-T digital cross connect on the configuration of
FIG. 2
is shown in FIG.
4
. Here the TSI for input port
1
does not change the positions of its input timeslots. The input TSI for port
2
, however, reorders its timeslots from E, F, G, H, to—, F, H, E. The G here is dropped as it is not used by any output ports. The space switch takes the outputs of the two input TSIs and switches them, without changing timeslots, to create the streams A, F, H, D and A, B, C, E. Note that this involves a multicast of timeslot A to both outputs. Finally, the output TSIs reorder these streams to give the output streams H, D, F, A and E, A, B, C.
A three-stage T-S-T digital cross connect is logically equivalent to a 3-stage Clos network with R T×T input stages, T R×R middle stages, and R T×T output stages. To route a configuration of input timeslots to output timeslots on such a switch a middle-stage timeslot must be assigned to each connection. This routing is described in detail in Clos, Charles, “A Study of Non-Blocking Switching Networks”, Bell System Technical Journal, March 1953, pp. 406-424, and V. E. Benes, “On Rearrangeable Three-Stage Connecting Networks”, The Bell System Technical Journal, vol. XLI, No. 5, September 1962, pp. 1481-1492.
SUMMARY OF THE INVENTION
Digital cross connects, including grooming switches, typically have several disadvantages. First, as illustrated in
FIG. 2
, the size of fully demultiplexed grooming switches typically increase quadratically with the number of timeslots times the number ports. For example, with the simple DEMUX/MUX architecture, multiplexed input traffic is demultiplexed into its constituent timeslots. For STS-48 traffic, 48 individual byte-wide buses corresponding to 48 timeslots must be input into the switch. Thus, if the port count is 72 ports, 3456 byte-wide buses must be coupled to the inputs of the switch. This results in some switch architectures being physically unrealizable due to size requirements.
With multi-staged switch architectures, as illustrated in
FIGS. 3 and 4
, the layout size issues are less dramatic. However, high latency, in the order of milliseconds, is associated with reconfiguration of input-output connections. Input-output connections are associations between input timeslots and output timeslots that define data paths through the switch in space and time. Such input-output connections may include input-output permutations and multicast connections. The source of such latency typically stems from complex scheduling computations used by multi-stage cross connects to reconfigure these connections. Such computations typically involve the selection of a middle-stage timeslot to route calls from a particular input timeslot to a particular output timeslot.
Embodiments of the invention provide a switch that switches streams of multiplexed traffic in both time and space domains. Such embodiments implement a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, such embodiments also result in low latencies being associated with reconfiguration of input-output connections on the ord

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