Encoding of failing bit addresses to facilitate multi-bit failur

Details Encoding of failing bit addresses to facilitate multi-bit failur Encoding of failing bit addresses to facilitate multi-bit failur

1998-03-19

2000-06-13

Baker, Stephen M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

714805, 714806, G06F 1120, G11C 2900, H03M 1302

Patent

active

060761768

ABSTRACT:
A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

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