4. Excavating

Christopher J. Cianciolo

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ESD protection clamp for mixed voltage I/O stages using NMOS tra

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent

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High speed method for maintaining cache coherency in a multi-lev

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Interface that permits data bus signals to pass between high fre

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
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Method and apparatus for performing switched supply drive in CMO

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent

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Method for addressing page tables in virtual memory

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Profile ID: LFUS-PAI-P-193171

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