High speed method for maintaining cache coherency in a multi-lev

Details High speed method for maintaining cache coherency in a multi-lev High speed method for maintaining cache coherency in a multi-lev

1995-01-27

2000-04-04

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711124, 711138, 711142, 711143, G06F 1212

Patent

active

060473576

ABSTRACT:
A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.

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