Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1993-07-19
1998-09-01
Shin, Christopher B.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
G06F 1208
Patent
active
058026045
ABSTRACT:
A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables. Since consecutive pages of the page table in virtual memory reside in consecutive page frames in physical memory, a virtual address in the page tables can be translated to a physical address by adding the page frame number from the prototype page table entry to the virtual page number in the virtual address. The prototype page table entry contains a page-frame number that is equal to the page-frame number of the first page of the page table minus the virtual-page number of the first page of the page table.
REFERENCES:
patent: 5239635 (1993-08-01), Stewart et al.
Lee Sherry Tsi-chuan
Leonard Timothy Edwin
Stewart Robert E.
Cianciolo Christopher J.
Digital Equipment Corporation
Shin Christopher B.
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