4. Error detection/correction and fault detection/recovery
  5. Data processing system error or fault handling
  6. Reliability and availability

Brent Lindsay

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Method and apparatus for high-speed edge-programmable timing...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate

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Method and apparatus for high-speed edge-programmable timing...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate

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Method and apparatus for testing memory devices and displaying r

Excavating
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Method and apparatus for testing memory devices and displaying r

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Method and apparatus for testing memory devices and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Profile ID: LFUS-PAI-P-708954

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