Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-09-01
2001-08-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C327S298000, C708S272000
Reexamination Certificate
active
06271682
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly to a method and apparatus for generating electronic signals for controlling operation of semiconductor devices.
BACKGROUND OF THE INVENTION
Those of ordinary skill in the field of semiconductor devices will be familiar with many different types of such devices, including, for example, microprocessors and various types of memory devices, such as dynamic random-access memory devices (“DRAMs”), synchronous DRAMs (“SDRAMS”), static random-access memory devices (“SRAMS”), and the like, capable of storing millions of bits of digital information.
In many cases, semiconductor devices are required to be operated at very high speeds. For example, the clock signal controlling operation of a microprocessor may be an oscillating square wave having a frequency of several hundred megahertz or more, such that the microprocessor is capable of executing hundreds of thousands or even millions of machine instructions each second. Likewise, semiconductor memory devices, whether synchronous or asynchronous, are preferably capable of being accessed (i.e., having data read from or written to) millions of times per second.
A typical semiconductor device operates by being responsive to a plurality of digital control signals applied to its control signal input terminals (often referred to as “pins”). (As used herein, the term “control signal” is intended to refer to essentially any electrical signal applied to a semiconductor device during operation thereof, including without limitation, control signals, clock signals, test signals, address and data signals and the like.) For example, a DRAM is responsive to a row address strobe (“RAS”) input control signal, a column address strobe (“CAS”) input control signal, a read/write (“R/W”) signal, and a plurality of address signals to access a particular memory location. To access a memory device, either to read data from a desired location in the memory or to write data to a desired location, external control circuitry manipulates the logic states of the various applied control signals. A RAS signal conditions a memory device to receive a row address applied to its address pins, a CAS signal conditions a memory device to receive a column address applied to its address pins, and the R/W signal conditions the device to perform either a read operation to, or a write operation from, the memory location specified by the received row and column address signals.
A semiconductor device may be responsive to the logic states of control signals, i.e., a logic “1” represented by a control signal having a “high” voltage of 3.3 to 5 volts, or a logic “0” represented by the control signal having a “low” voltage of zero volts. Alternatively, it is not uncommon for a semiconductor device to be responsive to “edges” of certain control signals, i.e., a rising edge transition from a logic “0” state to a logic “1” state, or a falling edge transition from a logic “1” state to a logic “0” state. As a simplified example, a transition from a logic “1” to a logic “0” in the applied RAS control signal, assuming the logic states of certain other applied control signals are appropriate, may define the initiation of a row address input interval during which time the memory device uses the address bits applied to its address pins to locate the row of memory to be accessed.
Those of ordinary skill in the art will appreciate that when semiconductor devices are to be operated at very fast rates, the timing of the various applied control signals must be very precise. Certain control signal timing tolerances, typically specified by semiconductor device manufacturers, must be observed in order to ensure proper device operation. Such tolerance parameters are typically defined for each signal relative to one or more other control signals applied to the device. As a generic example, it may be the case that an edge must occur in one signal within a predetermined period of time following the occurrence of an edge in some other applied signal. As another generic example, it may be specified that one particular control signal must be in a given state (high or low) for at least some predetermined period of time prior to the occurrence of an edge in some other signal. Often, these predetermined periods of time are quite small indeed, on the order of one to three nanoseconds, or in some cases even less.
Precision in control signal timing is important not only for the purposes of normal operation of semiconductor devices, but also—perhaps even more so—for the purposes of semiconductor device testing. Precisely controlling and varying control signal timing is important from the standpoint not only of ensuring that a device will operate properly if specified timing parameters are observed, but also of enabling a tester to determine what timing parameters should be specified for a device under test, or to determine to what extent a particular device might be tolerant to control signal timing variations beyond those specified for the device.
Various types of automated test equipment are known and available for conducting operational tests on individual semiconductor devices. Typically, such equipment is adapted to automatically run a semiconductor device through a sequence of test regimens during which one or more control signal timing parameters may be varied through a range of values. This enables the testing system to determine whether the device under test is tolerant to such variations within the ranges reflected in the device's specifications, and further to determine whether the device is tolerant to an even wider range of variations, such that different specifications may be provided for the device under test.
Those of ordinary skill in the art will appreciate that the implementation of circuits for generating the high-speed, precision control signals necessary either to operate or to test a semiconductor device can constitute a non-trivial engineering challenge. Implementing control signal generating circuitry for semiconductor device testing equipment is particularly challenging in view of the fact that it involves generating precisely-timed signals that themselves are capable of being variably time-adjusted with an even greater degree of precision.
One example of a control signal generator suitable for the purposes of semiconductor device testing is proposed in U.S. Pat. No. 4,675,546 to Shaw, entitled “Edge Programmable Timing Signal Generator.” The '546 patent appears to disclose an edge-programmable timing signal generator which makes use of predetermined and variable-length delay elements to which an input timing signal is applied. Varying the delay interval of one of the variable-length delay elements enables precision adjustment of the rising edge of the resultant output signal, while varying the delay interval of another of the delay elements enables precision adjustment of the falling edge of the output signal.
As noted in the '546 patent, there is a recognized desire for programmable timing signal generators which are simple in their design, and hence inexpensive, but nonetheless capable of outputting very precisely variable control signals.
SUMMARY OF THE INVENTION
In view of the foregoing and other considerations, the present invention relates to a method and apparatus for edge-programmable timing signal generation in which the timing of rising and falling edges in the timing signal can be very precisely controlled.
In one embodiment, binary digital data coarsely defining the desired timing of rising and falling edges in the timing signal to be generated is stored in a conventional semiconductor memory device. The memory device is accessed to obtain a plurality of data bits therefrom in parallel. The accessed data is applied to the input of a serializer to produce a serial data stream. The serial data stream is applied to the inputs of first and second programmable delay elements. Each delay element is adapted to introduce a delay into the serial data stream. The
Chang Daniel D.
Hugh Kress Winstead Sechrest & Minick
Micro)n Technology, Inc.
Tokar Michael
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