Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-09-20
2001-12-11
Trammell, James P. (Department: 2161)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06330693
ABSTRACT:
TECHNICAL FIELD
The present invention relates to apparatus and methods for testing electrical devices, particularly semiconductor memory devices.
BACKGROUND OF THE INVENTION
Various types of errors can occur during the manufacture of semiconductor devices. As circuit density on semiconductor devices increases, the number of these errors can increase. For quality control and to improve yields of commercially acceptable semiconductor devices, the semiconductor devices are tested, often before a die containing the device is packaged. A series of probes on a test station contact pads on the die to thereby access portions of the semiconductor device.
For example, in a semiconductor memory device, the probes contact address pads to access selected memory cells in the memory device. A predetermined set or pattern of data is typically written to selected addresses that correspond to certain memory cells, and then the data is read from those memory cells to determine if the read data matches the data written to that address. If the read data does not match the written data, then the memory cells at the selected addresses are likely faulty.
A person testing several dies on the wafer can then examine a particular die itself, by means of a microscope, to determine the reason for such errors, e.g., whether the errors occurred from masking defects, during deposition of certain layers, and so forth. During the initial development of a semiconductor device, many different changes can be made to compensate for detected errors, including making changes to certain masks. Once a semiconductor device is in production, however, redundant circuitry on the semiconductor device can be employed to compensate for only certain detected errors.
One known apparatus for testing semiconductor wafers, manufactured by Teradyne Corporation, employs a test bed that receives the wafer, probes that contact the pads on each die in the wafer, and testing circuitry for applying addresses and writing data to, and reading data from, the dies by means of the probes. An error catch memory stores comparison signals from an error compare circuit that reflect errors located in the semiconductor wafer (“error data”). The error catch memory also receives addresses from an address generator circuit of locations on the die at which the errors occurred, such as the row and column or “logical addresses” of memory locations in a memory cell. A host computer retrieves the error data and the logical addresses from the error catch memory and displays the error data on a visual display such as a raster display CRT.
The host computer in the Teradyne apparatus maps the error data to spatial locations on the display device that correspond to physical locations on the die. As a result, the visual display shows an enlarged view of the die containing the semiconductor device and the locations on the semiconductor device that produced the error data (e.g., the locations of faulty memory cells). The person testing the semiconductor device can then see the locations of the errors on the device from the visual display and therefrom know where to inspect on the die to examine certain memory cells that produced the errors. The person can thereby possibly uncover manufacturing defects in the die.
Often, semiconductor devices employ logical addressing schemes that do not correspond to X and Y axis spatial locations on a visual display device. In a bitmapped display, the top leftmost pixel typically has a minimum coordinate value such as (0,0), while the lower right-hand pixel has a maximum coordinate value such as (528, 727). In a typical memory deice, employing only a single array of memory cells, a lower right comer of the array instead could have a minimum logical row and column address of (0,0) for the first bit in the device, while the upper right could have a maximum logical address that corresponds to the size of the array. A simple mapping algorithm is necessary to map the memory array locations to bitmap coordinates on the visual display.
Many complex memory devices produced today employ
16
or more arrays of memory cells on a single semiconductor device. Each array in the semiconductor device could itself have a logical addressing scheme that differs from those of neighboring arrays on the device. As a result, the host computer in the Teradyne apparatus must perform even more complex algorithms to map the logical addresses at which the errors occurred on the semiconductor device to spatial locations or “spatial addresses” on the visual display, which correspond to physical locations on the die at which the errors occurred. In other words, the host computer in the Teradyne apparatus must convert the logical addresses of a semiconductor device being tested to physical addresses, which correspond to physical locations on the device, and then convert the physical addresses to spatial addresses for bitmap display on the display device.
The complex algorithm employed by the host computer is inherently slow, particularly when many mapping algorithms must be performed for many addresses in a complex semiconductor memory device. If a person conducting the test desires to change addresses on the semiconductor device or input different parameters (e.g., higher voltage values), these addresses/parameters must be input to the testing circuitry, the testing circuitry initiated, and then the host computer must again perform the mapping algorithms to display new error data on the visual display. This process is inherently time consuming as a result of the logical-to-physical and physical-to-spatial mapping algorithms required to properly display error data on the display device. With a large number of dies to test on a single semiconductor wafer, and many memory locations on a given die itself to test, the time consuming process required by the Teradyne testing apparatus requires many man hours.
The time consumptive nature of this prior art method is exacerbated by the need to reload a different routine or employ a different testing circuit for different semiconductor devices, some of which may be on a single wafer. Therefore, if a memory device employing four memory cell arrays is initially tested, and then a memory device employing 16 memory cell arrays is later tested, a different algorithm must be loaded into the host computer and the testing circuitry must be modified for the new memory device before the 16 array device can be tested.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for testing a semiconductor device, and in real-time, displaying the spatial locations of errors on a display device, where the locations of the errors on the display device correspond to physical locations on a die containing the semiconductor device. The present invention preferably employs a field programmable gate array (“FPGA”) or hardware implemented look-up table for rapidly routing the error data received from an error compare circuit to an error catch memory in a manner such that the error data is stored in the error catch memory at physical addresses that correspond to logical addresses employed by the device being tested. As a result, the router circuit continually routes error data to particular physical locations in the error catch memory. A topological circuit, such as an FPGA, remaps the physical locations of the error data from the error catch memory to spatial locations for display on a bitmapped display device such as a CRT. Therefore, the topological circuit can also continually route the error data from the error catch memory, through the host computer, for display on the display device. Overall, the router circuitry continually routes the logical addresses of error data to appropriate physical addresses in the error catch memory for the device being tested, while the topological circuitry continually maps the physical addresses of the error data to spatial addresses for display on the bitmap display device, all while the host computer is performing other functions such as applying a test pattern to the device, control
Dorsey & Whitney LLP
Elisca Pierre Eddy
Micro)n Technology, Inc.
Trammell James P.
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