Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-05-04
2000-12-26
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438404, 438424, 438430, H01L 21336, H01L 2176
Patent
active
061658545
ABSTRACT:
The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.
REFERENCES:
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5521422 (1996-05-01), Mandelman et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5897361 (1999-04-01), Egawa
patent: 5989977 (1999-11-01), Wu
patent: 6020230 (2000-02-01), Wu
Wolf, S.and Tauber, R.N., Silicon Processing for the VLSI Era, vol. 1, Lattice Press pp. 532-534, 546,1986.
A.E.T. Kuiper et al., Oxidation Behaviour of LPCVD Silicon Oxynitride Films, Applied Surface Science 33/34 (1988), pp. 757-764.
Andres Bryant et al.,Characteristics of CMOS Device Isolation for the ULSI Age, 1994 IEEE, pp. 671-674.
O.Joubert et al., Polysilicon Gate Etching in High-Density Plasmas: Comparison Between Oxide Hard Mask and Resist Mask, J. Electrochem. Socx., vol. 144, No. 5, May 1997, pp. 1854-1861.
Jones Josetta
Niebling John F.
Texas Instruments - Acer Incorporated
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