Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-25
2000-12-26
Pham, Long
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438229, 438275, 438276, H01L 218238
Patent
active
061658251
ABSTRACT:
LOCOS layers for defining NMOSFET and PMOSFET forming regions Rn and Rp are formed, and then a protective oxide layer is formed. A first resist layer, opened above the region Rn, is then formed on the protective oxide layer. By using the first resist layer as a mask, ion implantation is performed twice to form a threshold control layer and a P- layer functioning as a punch-through stopper or the like. By using the first resist layer as a mask, the substrate is etched to remove a portion of the protective oxide layer. Then, the first resist layer is removed. These processes are also performed on the region Rp. Then, a gate oxide layer is formed. Thus, it is possible to prevent a foreign impurity, introduced during the ion implantation, from diffusing the surrounding regions when the resist layers are removed. As a result, the properties of the gate oxide layer can be improved.
REFERENCES:
patent: 5283200 (1994-02-01), Okamoto
patent: 5527722 (1996-06-01), Hutter et al.
patent: 5824560 (1998-10-01), Van Der Wel et al.
Matsushita Electronics Corporation
Pham Long
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