OTP (open trigger path) latchup scheme using buried-diode for su

Details OTP (open trigger path) latchup scheme using buried-diode for su OTP (open trigger path) latchup scheme using buried-diode for su

1998-10-30

2000-04-25

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438218, 438221, 438231, 438232, H01L 218238

Patent

active

060543442

ABSTRACT:
Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the V.sub.dd and V.sub.ss power rails caused by the latchup of parasitic and complementary bipolar transistor structures that are present in CMOS devices. These goals have been achieved without the use of guard rings by using p-region implants in the n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors. Further, the p-region implants are shorted to a reference voltage V.sub.ss via a p.sup.+ ground tab thus backbiasing the diode-like p-region implants. The proposed methods are compatible with CMOS processes.

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