Memory device voltage steering technique

Details Memory device voltage steering technique Memory device voltage steering technique

1999-02-09

2000-12-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518525, 36518903, 36518518, 365203, 365204, G11C 700

Patent

active

061575771

ABSTRACT:
A method and associated circuitry are disclosed for applying the high column voltage needed to erase and program (write) a flash EEPROM memory. Low voltage CMOS transistors are used for both the read column precharge path and the write/erase data transfer path. This reduces precharge time, increasing the frequency at which the flash memory can be read. This also eliminates the lengthening of precharge time that occurs as the characteristics of high voltage transistors degrade with age. The present invention provides the additional advantage of eliminating the need to use less reliable high voltage transistors in certain off-pitch circuits needed for write and erase functions, thus increasing overall chip reliability.

REFERENCES:
patent: 4794564 (1988-12-01), Watanabe
patent: 5058063 (1991-10-01), Wada et al.
patent: 5450357 (1995-09-01), Coffman
patent: 5677872 (1997-10-01), Samachisa et al.
patent: 5790460 (1998-08-01), Chen et al.
patent: 5835415 (1998-11-01), Harari

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