Method to fabricate large capacitance capacitor in a semiconduct

Details Method to fabricate large capacitance capacitor in a semiconduct Method to fabricate large capacitance capacitor in a semiconduct

1997-06-04

1998-03-17

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

057286183

ABSTRACT:
A high capacitance stacked capacitor is defined using one optical mask for two masking steps where one masking step includes overexposing the resist layer. The method begins by forming a planarizing layer 28 over the substrate surface. A first photolithographic process using a first optical mask is used to form a first opening in the planarizing layer 28. A polysilicon stud 38 is formed in the first opening. A dielectric layer 40 is formed over the planarizing layer 28. A second opening 44 is formed in the dielectric layer 40 using a second photolithographic process using the same first optical mask. The second photoresist layer is exposed at a higher energy than the exposure of the first photoresist layer. The dielectric layer 40 is etched using the second photoresist pattern as an etch mask and forming the second opening 44 in the dielectric layer 40. Because of the overexposure, the second opening 44 has a larger open dimension than the first opening 36. A second polysilicon layer 50 is formed over the dielectric layer 40, over the sidewalls of the dielectric layer 40, and over the polysilicon stud 38 thus forming a cylindrical electrode 50A. The polysilicon plug 38 and the cylindrical electrode 50A comprise the bottom electrode 38 50A of the capacitor of the invention.

REFERENCES:
patent: 5126280 (1992-06-01), Chan et al.
patent: 5389568 (1995-02-01), Yun
patent: 5405796 (1995-04-01), Jones, Jr.
patent: 5468670 (1995-11-01), Ryou
patent: 5478769 (1995-12-01), Lim

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