Method for planarizing the interface of polysilicon and silicide

Details Method for planarizing the interface of polysilicon and silicide Method for planarizing the interface of polysilicon and silicide

1998-07-24

2000-09-12

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438488, 438597, 438654, 438652, H01L 213205

Patent

active

061177555

ABSTRACT:
A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped polysilicon layer is deposited on a semiconductor substrate in the integrated circuits, then immediately after the deposition of an undoped polysilicon, the process temperature is reduced and the treatment of purging is followed with, finally, a metal silicide is formed on the undoped polysilcion.

REFERENCES:
patent: 4992391 (1991-02-01), Wang
patent: 5256894 (1993-10-01), Shino
patent: 5441904 (1995-08-01), Kim et al.
patent: 5554566 (1996-09-01), Lur et al.
patent: 5849629 (1998-12-01), Stamper et al.
patent: 5877074 (1999-03-01), Jeng et al.

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