Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-12-01
2000-09-12
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438437, 438653, 438682, 438683, 438952, H01L 21336
Patent
active
061177431
ABSTRACT:
A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.
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Chen Coming
Lin Tony
Yeh Wen-Kuan
Hack Jonathan
Niebling John F.
United Microelectronics Corp.
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