Method of forming a trench MOS gate on a power semiconductor dev

Details Method of forming a trench MOS gate on a power semiconductor dev Method of forming a trench MOS gate on a power semiconductor dev

1997-12-22

2000-09-12

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438702, 438585, 438589, H01L 21336, H01L 213205

Patent

active

061177342

ABSTRACT:
A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.

REFERENCES:
patent: 4735824 (1988-04-01), Yamabe et al.
patent: 4839306 (1989-06-01), Wakamatsu
patent: 4983535 (1991-01-01), Blanchard
patent: 5599722 (1997-02-01), Sugisaka et al.
patent: 5783491 (1995-02-01), Nakamura et al.

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