Fabrication method of semiconductor device with CMOS structure

Details Fabrication method of semiconductor device with CMOS structure Fabrication method of semiconductor device with CMOS structure

1998-04-28

1999-06-01

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438510, 438527, 438919, H01L 218238, H01L 2104, H01L 21425

Patent

active

059083093

ABSTRACT:
A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region. The second acceleration energy is set in such a way that bottoms of the second pair of p-type source/drain regions in the PMOS region are not substantially shifted due to ion implantation of the n-type dopant for forming the second plurality of amorphous regions.

REFERENCES:
patent: 5273914 (1993-12-01), Miyajima et al.
patent: 5290712 (1994-03-01), Sato et al.

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