Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-04-09
2000-02-01
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 32, G01R 3128, G06F 1100
Patent
active
060215151
ABSTRACT:
A pattern generator to be used in a semiconductor test system for testing a semiconductor device having function modules common to other semiconductor devices and specific function modules unique to the semiconductor device under test includes, a first pattern generation block for generating test patterns for testing the common function modules in the semiconductor device under test, a second pattern generation block for generating test patters for testing said specific function modules in the semiconductor device under test, and a pattern combine circuit which is connected to the outputs of the first and second pattern generation blocks and transmits the test patterns from either one of the first or second pattern generation block, wherein the first pattern generation block sends a start signal to the second pattern generation block to initiate the operation of generating the module specific test patterns, and the second pattern generation block sends an end signal to the first pattern generation block to initiate the operation of the first pattern generation block.
REFERENCES:
patent: 4583041 (1986-04-01), Kimura
patent: 5029171 (1991-07-01), Lee et al.
patent: 5432797 (1995-07-01), Takano
Advantest Corp.
Tu Trinh L.
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