Static information storage and retrieval – Read/write circuit – Testing
Patent
1990-11-29
1994-12-27
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
36523003, 371 212, 371 251, G11C 700
Patent
active
053771486
ABSTRACT:
The present invention provides a test method of the complexity of 7n to test RAM devices, where n is the number of bits. This method tests all cell stuck-at-1/0 faults, state transition 1-to-0 and 0-to-1 faults, state coupling faults between two cells and data retention faults in random access memories. A standardized testable design memory (STD architecture) is presented which keeps the time required to test a RAM constant irrespective of the memory size. The design is shown through four examples to cover both bit and byte oriented memories. The memory address decoder is implemented in two or more levels. The decoder decoding the most significant addressed is modified by addition of an external control signal line. Memory of the RAM (memory cell array) is partitioned into blocks. The size of these blocks is defined by the last level (least significant address) of the memory address decoder. The design is highly structured and requires a very small amount of extra hardware. The architecture is not only applicable at chip level, but also at the board level. A slight modification allows fault diagnosis to be achieved in the STD architecture. This architecture also permits disconnection of faulty memory blocks and use the good part as 3/4 or 1/2 of the original capacity. Such reconfiguration in STD architecture can be done by specifying a fixed voltage (Gnd or Vdd) at the input of the most significant decoder. Such a reconfiguration does not require special hardware.
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Case Western Reserve University
Glembocki Christopher R.
LaRoche Eugene R.
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