Method and circuitry for preconditioning shorted rows in a nonvo

Details Method and circuitry for preconditioning shorted rows in a nonvo Method and circuitry for preconditioning shorted rows in a nonvo

1993-08-11

1994-12-27

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, 365210, 365900, 365218, 371 103, G11C 1140

Patent

active

053771478

ABSTRACT:
Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned. The other reference cell, a shorted reference cell, has a threshold voltage less than the nominal threshold voltage, but sufficient to prevent the quick overerasure of array cells during erasure. When the array cell is shorted to another cell within the array, selection circuitry selects the shorted reference cell. Otherwise, the other reference cell is selected.

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