Source synchronization data transfers without resynchronization

Details Source synchronization data transfers without resynchronization Source synchronization data transfers without resynchronization

1996-05-28

1999-07-06

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

395559, G06F 104

Patent

active

059192658

ABSTRACT:
A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC.sub.-- CLK) signal and a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC.sub.-- SYN.sub.-- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC.sub.-- SYN.sub.-- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC.sub.-- SYN.sub.-- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle. In one embodiment, data from two streams can be multiplexed and combined into a single data signal at the source subsystem, thereby increasing the bandwidth of the computer system to twice the frequency of the system clock generator.

REFERENCES:
patent: 4811364 (1989-03-01), Sager et al.
patent: 4881165 (1989-11-01), Sager et al.
patent: 5692166 (1997-11-01), Milhizer et al.
patent: 5706484 (1998-01-01), Mozdzen et al.

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