Process for fabricating a flash memory with dual function contro

Details Process for fabricating a flash memory with dual function contro Process for fabricating a flash memory with dual function contro

1998-01-16

1999-12-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, 438529, H01L 218247

Patent

active

060016892

ABSTRACT:
A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

REFERENCES:
patent: 5273923 (1993-12-01), Chang et al.
patent: 5306658 (1994-04-01), Gill
patent: 5474947 (1995-12-01), Chang et al.
patent: 5837584 (1998-11-01), Lu et al.

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