Erasable programmable memory

Details Erasable programmable memory Erasable programmable memory

1993-11-05

1995-02-28

Sikes, William L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257317, H01L 29788

Patent

active

053940024

ABSTRACT:
According to the invention, an electrically-erasable, electrically programmable read-only memory cell is formed at the face of a semiconductor layer 321 of a first conductivity type. A source region 311 and a drain region 312 are formed at the face of semiconductor layer 321 to be of a second conductivity type opposite the first conductivity type. Source region 311 and drain region 312 are spaced by a channel 313. A tunneling oxide window 327 is formed adjacent source region 311. A floating gate 314 is formed insulatively adjacent the entire length of channel 313 between source region 311 and drain region 312. Floating gate 314 is also formed directly adjacent tunneling oxide window 327. A control gate 315 is disposed 15 insulatively adjacent floating gate 314.

REFERENCES:
patent: 4590504 (1986-05-01), Guterman
patent: 4750024 (1988-06-01), Schreck
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 4912676 (1990-03-01), Paterson et al.
patent: 4924437 (1990-05-01), Paterson et al.
patent: 4935791 (1990-06-01), Namaki et al.
patent: 5017980 (1991-05-01), Gill et al.

Affiliated with

Also associated with

Rating

Erasable programmable memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Erasable programmable memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Erasable programmable memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-850146