Method of producing an MOS transistor

Details Method of producing an MOS transistor Method of producing an MOS transistor

1998-01-12

1999-12-07

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438299, H01L 21336

Patent

active

059982713

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

MOS transistors that are operated with supply voltage V.sub.dd <2 Volts are increasingly utilized for battery-operated circuit applications as well as for logic circuits with high packing density. Gate lengths and cut-off voltages must be correspondingly scaled in order to assure an adequate current yield (performance) given such supply voltages. Typical gate lengths of such MOS transistors typically lie below 1/4 .mu.m. The cut-off voltages V.sub.t are <0.3 volts. High demands made of the short channel behavior of the MOS transistors are connected therewith. These demands cause shallow source/drain regions having a depth below 100 nm and a technology with gate electrodes optimized with respect to the work function. Usually, n.sup.+ -doped polysilicon gate electrodes for n-channel MOS transistors and p.sup.+ -doped gate electrodes of polysilicon for p-channel MOS transistors (what is referred to as dual work function gate technology) is employed for optimizing the work function of the gate electrodes.
Since, in dual work function gate technology, the gate electrodes of polysilicon and the source/drain zones of the respective transistor are doped of the same conductivity type, gate electrode and source/drain zones can be fundamentally simultaneously doped by an ion implantation. Since, however, the gate electrode must also be highly doped given MOS transistors with shallow source/drain zones in order to avoid sacrifices in the current yield due to dopant depletion in the gate (gate depletion; see, for example, C. Y. Wong et al., IEDM '88, p. 238), the demands for the formation of shallow source/drain zones and highly doped gate electrodes by implantation are so different that this possibility is out of the question for MOS transistors with shallow source/drain zones.
A spread of the implantation profile that limits the minimum depth of shallow doped zones occurs in the ion implantation due to various effects. As a result of what is referred to as the channeling effect, a not inconsiderable part of the dopant penetrates more deeply into the crystal than corresponds to the range of the ions. The channeling tail that is thereby formed spreads the implantation profile. Since this effect is a result of the regularities in the crystal lattice, it has been proposed (see R. B. Fair, IEDM '87, p. 260) to render the region in the silicon in which the doped region is formed amorphous by an additional implantation with silicon or germanium before the implantation of dopant (what is referred to as pre-amorphization). The crystal damage produced in the implantation of silicon of germanium must be cured in additional tempering steps after the doping.
The implantation profile is also spread in that silicon inter-lattice atoms that produce an increase in the diffusion rate, particularly given the dopants of boron and phosphorus, are formed in the implantation (see P. B. Griffin et al., IEDM '93, p. 295).
In known methods for manufacturing MOS transistors with shallow source/drain zones, the doping of gate electrode and source/drain zones is optimized in two steps.
T. Eguchi et al., IEDM '93, p. 831, discloses a method wherein the gate electrodes are formed from polysilicon doped in situ. The source/drain zones are formed by implantation after structuring the gate electrodes. An added outlay of 1 to 2 photoresist masks derives in this process.
D. C. M. Yu et al., IEDM '94, p. 489, discloses a method wherein the source/drain zones and the gate electrode are respectively formed in a separate implantation step. In the source/drain implantation, the ion beam is angled and beam in with extremely low energy. A separate mask is required for each of the implantations.
T. Hori, IEDM '94, p. 75, discloses a method for the manufacture of an MOS transistor with shallow source/drain zones wherein the depth of the source/drain zones is subsequently reduced by an additional, angled counter-implantation. The gate electrode is covered by an additional mask in this counter-implantation.
M. Togo et al., VLSI

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