Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-29
1999-12-07
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438258, 438682, H01L 218241
Patent
active
059982527
ABSTRACT:
A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is achieved. Field oxide areas are formed to isolate a logic device area and a memory device area. A gate oxide layer, first polysilicon layer, silicon oxide layer and silicon nitride layer are deposited over the substrate. The silicon nitride layer is selectively removed in the logic device area. The layers in the memory device area are patterned to form memory devices. The layers in the logic device area are patterned to form gate electrodes. Silicon nitride spacers are formed on the sidewalls of the gate electrodes and memory devices and associated source and drain regions are formed within the substrate. The substrate is covered with a resist protective oxide which is removed in the logic device area. A layer of titanium is deposited over the substrate and transformed by annealing into a titanium silicide layer over the gate electrodes and associated source and drain regions. The unreacted titanium layer overlying the spacers, field oxide, and resist protective oxide layer is removed. An insulating layer is deposited over the substrate. A self-aligned contact opening is formed in the memory device area through the insulating layer between two of the memory devices to one of the associated source and drain regions. A second polysilicon layer is deposited over the substrate and within the self-aligned contact opening and patterned to complete the self-aligned contact.
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Ackerman Stephen B.
Lattin Christopher
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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