Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1993-12-27
1994-11-29
Mottola, Steven
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518912, G11C 702
Patent
active
053696123
ABSTRACT:
A semiconductor memory device comprising a memory cell array having a plurality of dynamic memory cells, each of the memory cells including a plurality of MOS transistors connected by cascade connection, capacitors for storing data each having an end connected to an end of a corresponding one of the MOS transistors, and a register arranged in a column portion of the memory cell array, for temporarily registering the data read from the memory cells in a time series manner.
REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 4070590 (1978-01-01), Ieda et al.
patent: 4225945 (1980-09-01), Kuo
patent: 4583382 (1986-06-01), Fijishima et al.
patent: 4648073 (1987-03-01), Kenney
patent: 4669063 (1987-05-01), Kirsch
patent: 4683555 (1987-07-01), Pinkham
patent: 4758987 (1988-07-01), Sakui
patent: 4943944 (1990-07-01), Sakui et al.
patent: 4980863 (1990-12-01), Ogihara
patent: 5025294 (1991-06-01), Ema
patent: 5051954 (1991-09-01), Toda et al.
patent: 5079746 (1992-01-01), Sato
patent: 5091761 (1992-02-01), Hiraiwa et al.
patent: 5091885 (1992-02-01), Ohsawa
patent: 5172198 (1992-12-01), Aritome et al.
patent: 5184326 (1993-02-01), Hoffman et al.
Kimura et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-line Architecuture", ISCC 91, Slide Supplement, pp. 70-71 Feb. 1991.
Arimoto et al., "A Circuit Design of Intelligent CDRAM with Automatic Write back Capability", 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 79-80.
Shah et al., "A 4Mb DRAM with Cross-point Trench Transistor Cell", 1986 ISSCC Digest of Technical Papers, pp. 268-269.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", 1988 IEDM Technical Digest, pp. 592-595.
Watanabe et al., "Stacked Capacitor Cells for High-density Dynamic RAMs", 1988 IEDM Technical Digest, pp. 600-603.
Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 74/256 MBit DRAMs", 1989 IEDM Technical Digest, pp. 23-26.
Fujishima et al., "A Storage-Node-Boosted RAM with Word-Line Delay Compensation", IEEE Jouranl of Solid State Circuits, vol. SC-17, No. 5, pp. 872-875, Oct. 1982.
Ohta et al., "A Novel Memory Cell Architecture for High-Density DRAMs", 1989 Symposium of VLSI Circuits, Digest of Tech. Papers, pp. 101-102.
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High Density VLSI Dynamic Memory", IEEE Transactionss on Electron Devices, vol. ED-29, No. 3, Mar. 1982, pp. 368-376.
Kimura, et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture," ISSCC 91, pp. 106-107, Feb. 14, 1991.
Asakura et al., "Cell-Plate Line Connecting Complementary Bitline (C.degree.) Architecture for Battery Operating DRAMs", 1991 Symposium on VLSI Circuits, May 30, 1991, pp. 59-60.
Ohta, et al., "A Novel Memory Cell Architecture for High Density DRAMs", Sharp Technical Journal, vol. 44, Mar. 1990, Japan, pp. 47-50.
Kabushiki Kaisha Toshiba
Mottola Steven
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